Job Description

In this role, you ll be tasked with assessing and improving Xilinx-based FPGA emulation of the ASIC. You will review the current FPGA build environment, design constraints, and build/timing/utilization reports, identify improvements, and work with the Design team to implement updates that enable complete, accurate, functional, and stable builds on FPGA hardware.

• Review current FPGA build environment, design constraints and implementation, and build/timing/utilization reports
• Update design constraints (XDC) to match ASIC design constraints (SDC), including clock frequency scaling as needed to accommodate FPGA limitations
• Identify FPGA build environment improvements
• Ensure the FPGA design follows industry-standard best practices (clock and reset generation, bidirectional buffer usage, etc.)
• Assess viability of current FPGA hardware for the targeted RTL design
• Ensure the FPGA can build, meet timing, and pass on-board testing
• Collaborate with the RTL Design team, document work, and attend recurring status update meetings
• Use Git version control software daily

• Master s or Bachelor s degree in Electrical Engineering or similar field
• Experience setting up, constraining, optimizing, and closing timing on high-utilization designs
• Experience with Xilinx and Vivado

• Experience with Git version control software
• Experience with Jira project workflow software

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