ASIC/FPGA Validation Engineer Job at Openkyber, Georgia

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  • Openkyber
  • Georgia

Job Description

Job Responsibilities:
  • Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVM
  • Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions
  • Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
  • Enhance your leadership skills while contributing to a dynamic DV team
  • Create reusable Verification IP to be shared across the organization;
  • Support implementing upgrades to our process and methodologies.
  • Enhance your DV skills as well as your knowledge of Networking while working with subject matter experts;
  • Mentor junior engineers
  • Participate in the development and deployment of networking and satellite bus FPGAs
Job Qualifications:
  • Bachelor's degree in Computer Engineering/Science, Electrical Engineering, related discipline, or equivalent experience
  • 5+ years of experience in FPGA/ASIC design verification
  • Experience planning, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM
  • Experience developing and implementing test plans.
  • Experience with FPGA/ASIC design and verification tools (Synopsys, Vivado, Quartus)
  • Experience monitoring and optimizing design verification coverage wrt to line, FSM, functional, etc.
  • Experience deploying System Verilog Assertions to enhance verification and reduce debug time
Preferred Qualifications:
  • Strong communication and documentation skills
  • Working knowledge of Ethernet, Interlaken, PCI Express, SPI, UART, and I3C protocols
  • Understanding of TCP/IP Networking with specific familiarity of OSI layers 2-4

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